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YSS912C
AC3D2
Dolby Digital (AC-3) / Pro Logic / DTS decoder + Sub DSP
INTRODUCTION
The YSS912C is one chip LSI consisting two built-in DSP's ; Dolby Digital (AC-3) / Pro Logic / DTS decoder (Main DSP) and a sound processing DSP (Sub DSP). Sub DSP is capable of realizing various sound fields, such as virtual surround, by down-loading the program and coefficient. Sub DSP is compatible with YSS902, the Sub DSP programs developed for YSS902 are also applicable to YSS912C.
FEATURERS
Pin compatible with YSS902 (AC3D). Dolby Digital (AC-3) / Pro Logic and DTS decode. 24 bit DSP. (Group-A Dolby Digital decoder) No external memory is required (Memory for center and surround channel delay is included) when DTS decoding as well as AC-3 / Pro Logic. Possible to decode multi-language encoded data. (possible to decode based on data-stream-number) AC-3 karaoke mode. Original compression mode as well as four compression modes recommended by Dolby. (when AC-3 decoding) Included de-emphasis filter. Pro Logic decoding for Dolby digital 2 channels decoded signal as well as ordinary PCM. High performance 25 MIPS programmable DSP suitable for a variety of sound field processing such as original surround , filtering, virtual surround etc. Up to 1.36 second delay time is capable when used with an external 1Mbit SRAM. (at fs= 48 kHz) Reads Dolby Digital (AC-3)/DTS decode information through the microprocessor interface. Provide total sixteen I/O ports. Possible to connect most of SPDIF receivers, A/D and D/A converters, by setting I/O data interface format. Has a built-in PLL oscillation circuit to generates its own operating clock. Internal operating clock is 30 MHz. Supply Voltage: 3.3v for core logic. 5v for I/Os. Power saving mode. Si-gate CMOS process. 100 QFP.(YSS912C-F)
Note: "AC-3" and "Pro Logic" are registered trademarks of Dolby Laboratories Licensing Corporation. "DTS" is a registered trademark of DTS, Inc. Use of this LSI must be licensed by both Dolby Laboratories Licensing Corporation and DTS, Inc.
YSS912C CATALOG CATALOG No.:LSI-4SS912C2 1999. 3
YSS912C
PIN CONFIGURATION
VSS IPORT0 IPORT1 IPORT2 IPORT3 IPORT4 IPORT5 IPORT6 IPORT7 VDD2 VSS RAMOEN RAMWEN RAMA0 RAMA1 SDIA1 SDIA0 SDBCK0 SDWCK0 VDD2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
2
VDD1 OPORT0 OPORT1 OPORT2 OPORT3 OPORT4 OPORT5 OPORT6 OPORT7 VSS VDD2 RAMA9 RAMA8 RAMA7 SDOB2 SDOB1 SDOB0 SDBCK1 SDWCK1 VSS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VDD1 RAMCEN RAMA16 RAMA15 SDIB0 SDIB1 SDIB2 XI XO VSS AVDD SDIB3 TEST TEST OVFB DTSDATA AC3DATA SDOB3 CPO AVSS VDD2 SDOA2 SDOA1 SDOA0 RAMA14 RAMA13 RAMA12 RAMA11 RAMA10 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
VSS RAMD7 RAMD6 RAMD5 RAMD4 RAMD3 RAMD2 RAMD1 RAMD0 VDD1 RAMA2 SCK SI SO /CS /CSB RAMA3 TEST /IC RAMA4 VSS RAMA5 RAMA6 /SDBCK0 SURENC KARAOKE MUTE CRC NONPCM VDD2
< 100QFP TOP VIEW >
YSS912C
PIN FUNCTION
No. Name I/O O O O I+ I+ I+ I O I+ FUNCTION +5V power supply (for I/Os) External SRAM interface /CE External SRAM interface address 16 External SRAM interface address 15 PCM input 0 to Sub DSP PCM input 1 to Sub DSP PCM input 2 to Sub DSP Crystal oscillator connection (12.288 MHz) Crystal oscillator connection Ground +3.3 V power supply (for PLL circuit) PCM input 3 to Sub DSP Test terminal (to be open in normal use) Test terminal (to be open in normal use) Detection of overflow at Sub DSP Detection of DTS data Detection of AC-3 data PCM output from Sub DSP Output terminal for PLL, to be connected to ground through the external analog filter circuit Ground (for PLL circuit) +3.3 V power supply (for core logic) PCM output from Main DSP (C, LFE) PCM output from Main DSP (LS, RS ) PCM output from Main DSP (L, R) External SRAM interface address 14 External SRAM interface address 13 External SRAM interface address 12 External SRAM interface address 11 External SRAM interface address 10 Ground +5V power supply (for I/Os) Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Output port for general purpose Ground +3.3 V power supply (for core logic) External SRAM interface address 9 External SRAM interface address 8 External SRAM interface address 7 PCM output from Sub DSP PCM output from Sub DSP PCM output from Sub DSP Bit clock input for SDOA, SDIB, SDOB Word clock input for SDOA, SDIB, SDOB Ground +3.3 V power supply (for core logic) Detection of non-PCM data Detection of AC-3 CRC error Detection of auto mute Detection of AC-3 karaoke data 3 1 VDD1 2 RAMCEN 3 RAMA16 4 RAMA15 5 SDIB0 6 SDIB1 7 SDIB2 8 XI 9 XO 10 VSS 11 AVDD 12 SDIB3 13 TEST 14 TEST 15 OVFB 16 DTSDATA 17 AC3DATA 18 SDOB3 19 CPO 20 AVSS 21 VDD2 22 SDOA2 23 SDOA1 24 SDOA0 25 RAMA14 26 RAMA13 27 RAMA12 28 RAMA11 29 RAMA10 30 VSS 31 VDD1 32 OPORT0 33 OPORT1 34 OPORT2 35 OPORT3 36 OPORT4 37 OPORT5 38 OPORT6 39 OPORT7 40 VSS 41 VDD2 42 RAMA9 43 RAMA8 44 RAMA7 45 SDOB2 46 SDOB1 47 SDOB0 48 SDBCK1 49 SDWCK1 50 VSS 51 VDD2 52 NONPCM 53 CRC 54 MUTE 55 KARAOKE
O O O O A O O O O O O O O O O O O O O O O O O O O O O I+ I+ O O O O
YSS912C
No. Name 56 SURENC 57 /SDBCK0 58 RAMA6 59 RAMA5 60 VSS 61 RAMA4 62 /IC 63 TEST 64 RAMA3 65 /CSB 66 /CS 67 SO 68 SI 69 SCK 70 RAMA2 71 VDD1 72 RAMD0 73 RAMD1 74 RAMD2 75 RAMD3 76 RAMD4 77 RAMD5 78 RAMD6 79 RAMD7 80 VSS 81 VDD2 82 SDWCK0 83 SDBCK0 84 SDIA0 85 SDIA1 86 RAMA1 87 RAMA0 88 RAMWEN 89 RAMOEN 90 VSS 91 VDD2 92 IPORT7 93 IPORT6 94 IPORT5 95 IPORT4 96 IPORT3 97 IPORT2 98 IPORT1 99 IPORT0 100 VSS NOTE) Is: I+: O: Ot: A: I/O O O O O O Is O Is+ Is Ot Is Is O I+/ O I+/ O I+/ O I+/ O I+/ O I+/ O I+/ O I+/ O I I I I O O O O I+ I+ I+ I+ I+ I+ I+ I+ FUNCTION Detection of AC-3 2/0 mode Dolby surround encoded input Inverted SDBCK0 clock output (refer to Block diagram) External SRAM interface address 6 External SRAM interface address 5 Ground External SRAM interface address 4 Initial clear Test terminal (to be open in normal use) External SRAM interface address 3 Sub DSP Chip select Microprocessor interface Chip select input Microprocessor interface Serial data output Microprocessor interface / Sub DSP Serial data input Microprocessor interface / Sub DSP clock input External SRAM interface address 2 +5V power supply (for I/Os) External SRAM interface data (STREAM0 output when External SRAM is not in use) External SRAM interface data (STREAM1 output when External SRAM is not in use) External SRAM interface data (STREAM2 output when External SRAM is not in use) External SRAM interface data (STREAM3 output when External SRAM is not in use) External SRAM interface data (STREAM4 output when External SRAM is not in use) External SRAM interface data (STREAM5 output when External SRAM is not in use) External SRAM interface data (STREAM6 output when External SRAM is not in use) External SRAM interface data (STREAM7 output when External SRAM is not in use) Ground +3.3 V power supply (for core logic) Word clock input for SDIA, SDOA, SDIB, SDOB Bit clock input for SDIA, SDOA, SDIB, SDOB AC-3 bitstream (or PCM) data input for Main DSP AC-3 bitstream (or PCM) data input for Main DSP External SRAM interface address 1 External SRAM interface address 0 External SRAM interface /WE External SRAM interface /OE Ground +3.3 V power supply (for core logic) Input port for general purpose Input port for general purpose Input port for general purpose Input port for general purpose Input port for general purpose Input port for general purpose Input port for general purpose Input port for general purpose Ground
Schmidt trigger input terminal Input terminal with a pull-up resistor Digital output terminal Tri-state digital output terminal Analog terminal
4
/CSB
OPORT0-7
YSS912C
BLOCK DIAGRAM
IPORT0-7 SCK SO SI SCK SI
Coefficient / Program RAM Control signals SDBCK1 SDWCK1
Microprocessor Interface
/CS
Control signals
Control Registers
/SDBCK0
SDBCK0 SDWCK0 SDOACKSEL
L, R
SDIBCKSEL
SDOBCKSEL
SDOB0 SDOB1 SDOB2 SDOB3
SDIA0
decoder
C, LFE
SDIBSEL
LS, RS
24 * 16 Sub DSP
SDIASEL
Delay RAM ERAMUSE
24 * 24 Main DSP
SDIB Interface
Input Buffer
SDOB Interface
SDOA Interface
AC-3/Pro Logic/DTS
SDIA Interface
SDIA1
STREAM0-7 External RAM interface Data RAM
Operating clock (30MHz)
CRC
SURENC KARAOKE MUTE CRC AC3DATA DTSDATA NONPCM
PLL
SDIB3 SDIB2 SDIB1 SDIB0
SDOA2 SDOA1 SDOA0
RAMD0-7
OVFB RAMA0-16 RAMOEN RAMWEN RAMCEN
XI
XO
CPO
5
YSS912C
FUNCTION DESCRIPTION
The YSS912C consist of Main DSP section where AC-3/Pro Logic/DTS decoding is executed and Sub DSP section where various sound field effects are added. Please refer to "BLOCK DIAGRAM" section. Sub DSP is a 8 ch input / 8 ch output programmable DSP exclusively for the sound field processing. It can apply such effects as virtual surround, echo and equalizing. In addition, with an SRAM up to 1Mbit connected, it can produce reverberation for one second or longer. By using this function, it is possible to simulate various sound fields such as a hall or a church. * If adopting some technology owned by another company is desired for use in Sub DSP section, note that a separate contract may be required between the owner of that technology and the user with respect to adoption of the technology.
1. Clocks XI, XO, CPO The crystal oscillation circuit is formed by using XI and XO terminals. Connect a crystal of 12.288 MHz between XI and XO terminals. Connect an external analog filter between CPO terminal and Ground.
2. Data Interface
SDIA0, SDIA1, SDOA0-2, SDIB0-3, SDOB0-3, SDWCK0, SDBCK0, SDWCK1, SDBCK1, /SDBCK0
Main DSP section AC-3/PCM/DTS data should be fed from SDIA0 or SDIA1 terminal. These signals are processed by AC-3/Pro Logic/DTS decoding procedure in Main DSP section and then transmitted to Sub DSP section as well as outputted through SDOA0-2 terminals. Sub DSP section In Sub DSP section, various types of processing can be applied to the PCM data decoded in Main DSP section or inputted through SDIB0-3 terminals. Then, processed signals are outputted from each of SDOB0-3 terminals. Following parameters can be selected by changing the control register setting. Selection of Main DSP input signal (SDIA0, SDIA1) Selection of Sub DSP input signal (Main DSP output, SDIB0-3 input) Polarity of bit clock and word clock Format and bit count of input/output data For more information on the format of the input/output data, please refer to "Serial Data Interface" section.
. . . .
3. Microprocessor Interface /CS, /CSB, SCK, SI, SO The control registers can be read/written via the serial microprocessor interface by using /CS, SCK, SI, and SO terminals. Please refer to the following format diagram for the details of read/write timing.
6
YSS912C
Format diagram for read/write timing
When /CS=1, the SO output becomes high-impedance. * Be sure to set /CSB to "1" when making an access to the control register. The sound field processing program used for Sub DSP is down-loaded by using the /CSB, SCK, and SI terminals. Please refer to Application manual for the details of Sub DSP.
4. External Interface RAMA0-16, RAMD0-7, RAMCEN, RAMOEN, RAMWEN An external SRAM can be connected to Sub DSP.
5. General purpose I/O ports OPORT0-7, IPORT0-7 OPORT0-7 terminals are output ports for general purpose. Data written on the register (address 0x04) are outputted from these terminals. IPORT0-7 terminals are input ports for general purpose. Data inputted to these terminals can be read from the register (address 0x05).
6. Initial clear /IC This LSI requires initial clear when turning on the power.
7. LSI test terminals TEST Leave the test terminals open in normal use.
7
YSS912C
CONTROL REGISTER
The decoding system is controlled by reading and writing the control registers through microprocessor interface (/CS, SCK, SI and SO). Note : All bits are set to "0" by initial clear (/IC=0) except bit 4 of PLL/DSN register (0x00).
address
Name
PLL/DSN Register Mute Register SDIA Register SDOA Register OPORT Register IPORT Register
bit 7
PLLUSE LMUTEN SDIASEL
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
DSN2 - 0
DSPMUTEN
bit 0
0x00 0x01 0x02 0x03 0x04 0x05
(not used) DSNIGN CMUTEN RMUTEN RSMUTEN LSMUTEN LFEMUTEN PDOWN SDIAFMT1 - 0 SDIABIT1 - 0 SDOACKSEL SDOAFMT1 - 0 SDOABIT1 - 0 OPORT7 - 0 IPORT7 - 0 (Read only)
AMOFF SDIAWP SDIABP SDOAWP SDOABP
0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
PCM Register Noise Level Register Center Delay Register Surround Delay Register Noise Register FS Register L Volume Register C Volume Register R Volume Register LS Volume Register RS Volume Register LFE Volume Register Compression Register HDYNRNG Register LDYNRNG Register Mode Register
PCMDLY NOISELEV7 - 0 CDELAY2 - 0 SRDELAY3 - 0 NOISE PN/WN IMPULSE FS1 - 0 LVOL7 - 0 CVOL7 - 0 RVOL7 - 0 LSVOL7 - 0 RSVOL7 - 0 LFEVOL7 - 0 AIBON VOLON DITHOFF P11OFF HDYNRNG7 - 0 LDYNRNG7 - 0 PLDECON PLSRMOD DUALMOD1 - 0
EMPON
DIALOFF
COMPMOD1 - 0
PCM
OUTMOD2 - 0
0x30 0x31 0x32 0x33 0x34 0x35 0x36
COEF0-H Register COEF0-L Register COEF1-H Register COEF1-L Register SDIB Register SDOB Register ERAM Register
SDIBCKSEL SDIBSEL
SDOBCKSEL SDBUSE
ERAMUSE
COEF0-15 - 8 COEF0-7 - 0 COEF1-15 - 8 COEF1-7 - 0 SDIBFMT1 - 0 SDIBBIT1 - 0 SDOBFMT1 - 0 SDOBBIT1 - 0 MPCNT5 - 0
SDIBWP SDOBWP
SDIBBP SDOBBP
Note : Do not write "1" into the cross-hatched bits because they are used for testing the LSI.
8
YSS912C
The following registers of address 0x18 to 0x2F are read-only (write disabled). The contents of the registers of address 0x18 to 0x2A vary depending on input signal, AC-3 bitstream, DTS bitstream or PCM, as described below. 1) When input signal is AC-3 bitstream
address
Name Bitstream Register 0 Bitstream Register 1 Bitstream Register 2 Bitstream Register 3 Bitstream Register 4 Bitstream Register 5 Bitstream Register 6 Bitstream Register 7 Bitstream Register 8 Bitstream Register 9 Bitstream Register 10 Bitstream Register 11 Bitstream Register 12 Bitstream Register 13 Bitstream Register 14 Bitstream Register 15 Bitstream Register 16 Bitstream Register 17 Bitstream Register 18
bit 7
fscod
bit 6
bit 5
bsid
bit 4
bit 3
bit 2
bit 1
bit 0
0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A
frmsizecod
bsmod acmod cmixlev surmixlev lfeon dsurmod copyrightb origbs 0 0 0 0 0 0 0 dialnorm 0 0 0 dialnorm2 audprodie mixlevel roomtyp audprodi2e mixlevel2 roomtyp2 timecod1e 0 timecod1 timecod1 timecod2e 0 timecod2 timecod2 langcode langcod2e compre compr2e 0 0 0 0 langcod langcod2 compr compr2 dynrng dynrng2
2) When input signal is DTS bitstream
address
Name 0x18 Bitstream Register 0 0x19 Bitstream Register 1 0x1A Bitstream Register 2 0x1B Bitstream Register 3
bit 7 fscod
bit 6
bit 5 undefined
bit 4
bit 3
bit 2 RATE
bit 1
bit 0
undefined AMODE undefined undefined PCMR lfeon
The contents of registers of address 0x1C to 0x2A are undefined. 3) When input signal is PCM The contents of registers of address 0x18 to 0x2A are undefined. The registers of address 0x2B, 0x2C are not used. From the registers of address 0x2D to 0x2F, the following data can be read.
address
Name
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0x2D 0x2E 0x2F
Pc4 - 0 Pc Register undefined Data Stream Register STREAM7 STREAM6 STREAM5 STREAM4 STREAM3 STREAM2 STREAM1 STREAM0 DTSDATA AC3DATA 2/0MODE SURENC KARAOKE MUTE CRC NONPCM Status Register
Address 0x06, 0x07 and 0x37 to 0x7F are assigned for TEST. Never access to these registers. Please refer to Application manual for details of Control register.
9
YSS912C
SERIAL DATA INTERFACE
Data timing of the serial data interface is as follows.
Bit clock
(SDBCK0, SDBCK1) BP=0 BP=1
Word Clock
(SDWCK0, SDWCK1)
WP=0 WP=1
Lch (LS, C ch) Lch (LS, C ch)
Rch (RS, LFE ch) Rch (RS, LFE ch)
FMT=00 BIT=00 BIT=01 BIT=10 BIT=11
15 14 13 12 11 10 9
(No delay)
15 14 13 12 11 10 9
876
5
4
3 5
21 4 3 5
0 21 4 3 0 2 1 5 0 4 3 21 0
876
5
4
3 5
2 4
10 3 5 2 4 10 3 2 10 5 4 3 2 10
17 16 15 14 13 12 11 10 9
876
17 16 15 14 13 12 11 10 9
876
19 18 17 16 15 14 13 12 11 10 9
876
19 18 17 16 15 14 13 12 11 10 9
876
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
876
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
876
FMT=01 BIT=00
15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9 19 18 17 16 15 14 13 12 11 10 9 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
(EIAJ)
15 14 13 12 11 10 9 17 16 15 14 13 12 11 10 9 19 18 17 16 15 14 13 12 11 10 9 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
876 876 876 876
5 5 5 5
4 4 4 4
3
21 1 1 1
0 0 0 0
876 8 7 6
5
4
3 3 3 3
2 2 2 2
10 10 10 10
Data
(SDIA,SDIB, SDOA,SDOB)
BIT=01 BIT=10 BIT=11
32 3 3 2 2
54 5 5 4 4
876 876
FMT=10 BIT=00 BIT=01 BIT=10 BIT=11
15 14 13 12 11 10 9
(I2S)
15 14 13 12 11 10 9
876
5
4
3 5
2 4
1 3 5
0 2 4 1 3 0 21 5 0 4 3 2 10
876
5
4
3 5
2 4
10 3 5 2 4 1 3 0 2 1 5 0 4 3 2 1 0
17 16 15 14 13 12 11 10 9
876
17 16 15 14 13 12 11 10 9
876
19 18 17 16 15 14 13 12 11 10 9
876
19 18 17 16 15 14 13 12 11 10 9
876
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
876
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
876
Please refer to Application manual for details of SDIA, SDOA, SDIB, and SDOB registers.
10
YSS912C
ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings Parameter
Power Supply Voltage Input Voltage Storage Temperature
Symbol
VDD1 VDD2, AVDD VI Tstg
Min.
Max.
Unit
V V V C
Vss-0.5 Vss+7.0 Vss-0.5 VSS+4.6 Vss-0.5 VDD1+0.5 -50 125
2. Recommended Operating Conditions Parameter
Power Supply Voltage Operating Temperature
Symbol
VDD1 VDD2, AVDD TOP
Min.
4.75 3.0 0
Typ.
5.0 3.3 25
Max.
5.25 3.6 70
Unit
V V C
3. DC Characteristics (Condition: Under Recommended Operating Conditions) Parameter
Input Voltage H Level (1) Input Voltage H Level (2) Input Voltage L Level (1) Input Voltage L Level (2) Output Voltage H Level Output Voltage L Level Input Leakage Current Pull-up Resistor Power Consumption *1 *2
Symbol
VIH1 VIH2 VIL1 VIL2 VOH VOL ILI RU PD
Condition
*1 *2 *1 *2 IOH = -80 mA IOL = 1.6 mA Terminal without a pull-up resistor
Min.
0.7VDD1 2.2
Typ.
Max.
Unit
V V V V V V mA kW mW mW
0.2VDD1 0.8 VDD1-1.0 -10 25 100 300 0.4 10 100 120 430
VDD1 (5V) VDD2 (3.3V) Applicable to XI and /IC input terminals. Applicable to input terminals except XI and /IC terminals.
4. XI and /IC Parameter
XI clock frequency XI clock duty /IC pulse width
Symbol
Xin Xduty
Conditions
Min
40
Typ
12.288 50
Max
60
Unit
MHz % ns
ticw
Power voltage to be stabilized
500
11
YSS912C
EXTERNAL DIMENSIONS
C-PK100FP-1
24.80 20.00 0.40 0.30 0.15 80 51 0.05 (LEAD THICKNESS)
81
50
14.00 0.30
100
1 30
31
P-0.65TYP
0.30
0.10
2.95 MAX.
(2.40)
0-15
0 MIN. (STAND OFF)
1.20 0.20
The figure in the parenthesis ( ) should be used as a reference. Plastic body dimensions do not include burr of resin. UNIT: mm
12
18.80 0.40
YSS912C
Memo
13
YSS912C
IMPORTANT NOTICE
1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. These Yamaha Products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. Use of the Products in any such application is at the customer's sole risk and expense. 3. Yamaha assumes no liability for incidental , consequential, or special damages or injury that may result from misapplication or improper use or operation of the Products. 4. Yamaha makes no warranty or representation that the Products are subject to intellectual property license from Yamaha or any third party, and Yamaha makes no warranty excludes any liability to the Customer or any third party arising from or related to the Products' infringement of any third party's intellectual property rights, including the patent, copyright, trademark or trade secret rights of any third party. 5. Examples of use described herein are merely to indicate the characteristics and performance of Yamaha products. Yamaha assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. Yamaha makes no warranty with respect to the products, express or implied, including, but not limited to the warranties of merchantability, fitness for a particular use and title.
The specifications of this product are subject to improvement changes without prior notice.
AGENCY
Address inquiries to: Semiconductor Sales & Marketing Department Head Office 203, Matsunokijima, Toyooka-mura Iwata-gun, Shizuoka-ken, 438-0192 Electronic Equipment Business section Tel. 81-539-62-4918 Fax. 81-539-62-5054 2-17-11, Takanawa, Minato-ku, Tokyo, 108-8568 Tel. 81-3-5488-5431 Fax. 81-3-5488-5088 Namba Tsujimoto Nissei Bldg, 4F 1-13-17, Namba Naka, Naniwa-ku, Osaka City, Osaka, 556-0011 Tel. 81-6-6633-3690 Fax. 81-6-6633-3691 YAMAHA Systems Technology. 100 Century Center Court, San Jose, CA95112 Tel. 1-408-467-2300 Fax. 1-408-437-8791
Tokyo Office Osaka Office
U.S.A. Office
All rights reserved (c) 1999
Printed in Japan

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